The present invention relates to a new arrangement of parity check bits in a semiconductor memory in data processing electronic apparatus.
In recent times, semiconductor storage systems have been largely employed as the main memories in data processing apparatus. These memories which are produced as large-scale integrated circuits having high density and a high number of elements, have shown remarkable advantages over the usual memories employing magnetic elements, with regard to operating speed, fabrication costs, and reliability. However, their operation requires particular care, especially with regard to the very high precision needed in the control times of different operations and, therefore, in the intervals between subsequent timing clock pulses.
These memories are produced by arranging integrated memory circuital units on printed-circuit cards together with the related control and address circuits, thus building modules having a predetermined partial capacity, these modules being duplicated until the planned whole capacity of the memory is reached.
The so-called "check bit", or "parity bit", method for detecting an error in the recording of an information bit of a word has been long known and is in general use. It consists in appending to the information bits of the word a check bit, whose binary value is so chosen, that, for example, the number of the bits of value ONE is always even. If this condition is not satisfied, at the end of an operation, this means that a bit is affected by error.
This technique as it is employed in the present state of the art, usually is unable to detect a cause of error affecting not a single bit, but the whole word including the check bit: for instance, a false addressing, causing the whole word, and its check bit, to be written at a wrong address, or, as it may happen in semiconductor memories, when a wrong time interval between two clock signals may alter the recording of a whole word in the same way for all bits, including the check bit. This is important because, in the prior art, the control and address circuits are assembled on the same printed card carrying the integrated memory units wherein all information and check bits of a word are recorded. Thus, it may happen that any cause of malfunction of the circuits on the card, such as an assembling mistake, a faulty contact, noise, and so on, affecting, for instance, an address amplifier, may cause a wrong addressing of the whole word or, affecting a clock circuit, may cause the wrong recording of a whole word. These errors, being common both to the information bits and to the check bits, cannot be detected by the parity check.